1. Field of Invention
The present invention relates generally to a method for plasma etching semiconductor wafers. More specifically, the invention relates to a method for etching high K dielectric materials using a gas mixture comprising a halogen gas, a reducing gas, and a passivating gas.
2. Description of the Background Art
The evolution of integrated circuit designs continually requires faster circuitry, greater circuit densities and necessitates a reduction in the dimensions of the integrated circuit components and use of materials that improve electrical performance of such components. A field effect transistor that is used in forming an integrated circuit generally utilizes a gate structure having a polysilicon electrode deposited upon a gate dielectric that separates the electrode from an underlying layer of doped silicon. The underlying layer of doped silicon comprises the channel, source, and drain regions of the transistor. The gate dielectric is typically fabricated from a silicon dioxide (SiO2) layer and/or a layer or layers of materials having a high dielectric constant (high K) such as Al2O3, ZrO2, barium strontium titanate (BST), lead zirconate titanate (PZT), ZrSiO2, HfSiO2, HfSiON, TaO2, and the like.
Fabrication of the gate structure comprises plasma etching the high K gate dielectric and post-etch cleaning to remove etch residue. The high K dielectric is etched using a gas mixture comprising a halogen gas (such as chlorine) and a reducing gas (such as carbon-monoxide). The carbon from the reducing gas forms a residue that must be removed after etching is completed. Oxygen is present in the post-etch cleaning plasma that generally uses an oxygen plasma to remove the etch residue. During the cleaning process, oxygen diffuses into the silicon of the wafer and the polysilicon of the gate electrode. When the polysilicon electrode and underlying doped silicon layer are exposed to oxygen, the oxygen oxidizes them. Oxidation degrades electrical performance of the gate structure and the transistor. During the post-etch cleaning process, diffusion of oxygen leads to creation of silicon dioxide (SiO2) formations in the polysilicon electrode and underlying doped silicon layer. Such formations may render the gate structure of a transistor defective or inoperable.
Therefore, there is a need in the art for a high K material etching process that protects the polysilicon electrode and underlying silicon from oxidation.